Many of us have dreamed of controlling the world with a ZX-81 (what else is it good for?).
For standalone or portable applications, a TV or monitor display is quite bulky and power hungry. You need a portable low power display and that would be a job for the Z80/LCD display. A ZX-81 with some I/O or for that matter the EZ80 controller (a 7 chip ZX-81 compatible controller with a keyboard, a serial port which needs about 10-20 ma at 6V) makes a nice compact package easily tucked away. The terminal software can be MTERM running in the FAST mode at 1200 baud with a patch to the ZX-81 ROM to write characters to the LCD instead of DFILE. It would copy DFILE to LCD Display RAM and use scroll to read the whole screen on a 2 or 4 lines of 40 character LCD.
How about writing some software to adapt the MTERM communication program? You can develop and run it on a PC under XT2, the ZX-81 emulator with a patch to the PC com port to emulate the Timex/Sinclair 2050 modem.
I have attached the final version of the Z80/LCD interface circuit, new driver software, and a little demo for printing 2 strings. The main difference is that Z80/LCD design is now robust and tested on several system I have added extra code for using 4-bit operation. The latter was not to save I/O pins (there aren’t any to save on the CPU bus 8^) but because a number of surplus LCD’s only have 4 data pins available. I have checked the Z80/LCD V0.3 circuit and software on 2 different ZX-81s and 3 different LCD’s with no problems.
So here is the Z80/LCD V0.3 article.
Z80/LCD Assembly Source Code
[e-mail address omitted] or [e-mail address omitted]
Introduction
Interfacing an LCD to the ZX-81 generally uses an 8255 type parallel printer port for generating the data and control signals for the LCD. This requires 7 or 11 I/O lines depending on the data path width which is selected. It was clear from the 8255 MC code listing that there is a lot of software required to generate the various read/write/data and command control sequences. This makes the LCD more difficult to use and in practice means LCD software modules are used as simple black boxes without realizing the full potential of this LCD. In the case of a single chip controller like the 16C84, you don’t have any choice but to use I/O ports for interfacing the LCD. However Z80 I/O devices can connect directly to the CPU bus, thereby minimizing hardware and software complexity.
Here is a design to interface the industry standard Hitachi type 44780 alphanumeric LCD directly to the Z80 CPU bus. A standard Z80 I/O decoder circuit can not be used since it does not have the required control timing. The Z80/LCD circuit provides the required control timing and adds a wait state for Z80 CPUs with a maximum clock of 4 MHz.
The LCD uses the HD44780 (or equal) controller chip which uses 11 commands to translate ASCII data to a dot matrix display. The LCD interfaces through a 14 (or 9) pin connector with a parallel I/O device like a printer port or single chip micro I/O port. It is less commonly used with a CPU bus. The LCD controller was originally designed for the 6800 CPU and is therefore not directly compatible with the Z80 bus.
The LCD controller requires 4 or 8 data bits, a register select (RS) line, an R/W signal and an E (clock) signal. For simplicity, the 4-bit mode is used which is selected during LCD initialization.
The basic interface operation consists of generating a positive logic E signal with a minimum of 200 ns delay from the time the other bus signals are stable. The minimum duration for the E signal is 450 ns during which all other signals must be stable. Data is clocked in on the falling edge of E. Data, RS and R/W have a minimum hold time of 10 ns after the falling edge of the E signal.
The timing diagram shows the real timing as measured with a storage scope. This is different from the data handbook timing diagrams. I have tried two different ZX-81 units and 3 LCD’s all of which work fine Adding an inverter in the clock line would probably fix timing problems in other circuits if they should occur. It is a good idea to first read the LCD data sheet and check out the many excellent websites dealing with LCD applications. If you still have problems, call me.
The 74HC74 is configured as a 2 stage counter with stage 1 as a one wait state generator and the E signal generated by stage 2. The 2nd WAIT pulse in the diagram is ignored by the CPU. The diode which is “wired or” to the CPU WAIT line is only required for the ZX-81. A direct connection to the CPU WAIT input would be used in other Z80 applications. The 74HC138 in this design would normally be present for conventional I/O decoding so the only additional components are the 74HC74 and 1/6 of a 74HC04 chip and a diode.
The software was written to support both 9 and 14 pin LCD. This means all data bytes are transferred 4 bits at a time (nibbles). The pinouts for the LCD connectors are shown below. The 9-pin connector pins were found by experiment. The 14-pin connector is standard but please note that pin 3, which is the display contrast adjustment input (V0), has a value of 0 to +5V for normal LCD’s but 0V to -5V for extended temperature displays. For the normal LCD a 10K pot can be connected between Pin 1 and pin 2 with the wiper connected to pin 3.
Z80/LCD – A Z80 TO HD44870 LCD Interface
Beta version 0.3 (c) Oct 18, 1998
;ZX-81 LCD-PRINT STRING
;V0.2 OCT 18,1998
;W. RIGTER
;HD44780 2X20 CHAR LCD
;4 BIT INTERFACE
;ALL DATA IS TRANSFERRED
;IN 2 NIBBLES ON D4-D7
;EXCEPT INITIALIZATION
LCDDATA=9F ;LCD DATA ADDRESS
LCDCTRL=8F ;LCD CONTROL ADDRESS
ENTRY=06 ;INCREMENT/CURSOR SHIFT
START LD A,30 ;INIT CODE IN D4-7
LD B,3 ;WRITE FUNCTION 3X
INIT1 CALL DCW ;CMND WRITE WITH
DJNZ INIT1 ;DELAY LOOP
INIT2
LD A,20 ;4 BIT MODE SEND
CALL DCW ;IN 1 NIBBLE
;NOW ALL DATA IS SEND IN
;2 NIBBLES PER BYTE
LD A,28 ;4 BIT MODE, 2 LINE, 5x7
CALL CW ;COMMAND WRITE
LD A,08 ;DISPLAY OFF
CALL CW ;CMND WRITE
LD A,01 ;HOME+CLEAR DSPLY
CALL CW ;CMND WRITE
LD A,ENTRY ;ENTRY MODE
CALL CW ;CMND WRITE
;END OF INITIALIZATION
LD A,0F ;DSPLY ON,CURSR ON
CALL CW ;COMMAND WRITE
;WRITE 2 STRINGS TO LCD
LD A,80 ;SET DDRAM ADRS=00
CALL CW ;START OF LINE 1
LD HL,ASC1 ;STRING 1
CALL STRNG
LD A,C0 ;SET DDRAM ADRS=40
CALL CW ;START OF LINE 2
LD HL,ASC2 ;STRING 2
CALL STRNG
RET
STRNG LD A,(HL) ;GET EACH CHAR
INC HL
CP FF ;LAST CHAR
RET Z ;RETURN
CALL DW ;DATA WRITE
JR STRNG ;NEXT CHARACTER
;BUSY/DATA WRITE
DW CALL BUSY ;LCD READY?
OUT LCDDATA,A ;MSB DATA
RLA ;SHIFT LSB TO MSB
RLA
RLA
RLA
OUT LCDDATA,A ;LSB DATA
RET
;DELAY/COMMAND WRITE
DCW
PUSH AF ;SAVE COMMAND
LD DE,2000 ;DELAY TIME
DCW1 DEC DE ;SOFTWARE LOOP
LD A,D ;TEST FOR DE=00
OR E
JR NZ DCW1 ;IS DE=00?
POP AF ;GET COMMAND
OUT LCDCTRL,A ;MSB ONLY
RET
;BUSY/COMMAND WRITE
CW CALL BUSY ;LCD READY?
OUT LCDCTRL,A ;MSB COMMAND
RLA ;SHIFT OVER 4 BITS
RLA
RLA
RLA
CW1
OUT LCDCTRL,A ;COMMAND
RET
;TEST BUSY FLAG
BUSY
PUSH AF ;TEMP SAVE AF
BSY1 IN A,LCDCTRL ;RD BUSY FLAG
RLA ;SAVE BS IN CARRY
IN A,LCDCTRL ;NEXT NIBBLE
JR C BSY1 ;UNTIL BS = ZERO
POP AF ;RESTORE AF
RET
;ASCII="! ENJOY - WILF !"
ASC1 21 20 65 6E 6A 6F 79 20 FF
ASC2 B0 20 77 69 6C 66 20 21 FF[Figure: Z80/LCD Interface Schematic (74HC138 decoder, two 74HC74 flip-flops, 1N34A diode on /WAIT, 2×20 LCD (HD44780) with 10K contrast adjust; outputs 7/FE, 6/FC, 5/FA, 4/F8 user selectable; Command Address = 0F, Data Address = 1F)]
[Figure: Z80/LCD Interface Timing (CLK T1 T2 Tw Tw T3, /IORQ, /WR, /WAIT, E, A4 (RS), D0-7)]
9/14 PIN LCD Connectors
9-pin 14-pin Function
1 1 0V
2 2 5V
3 V0 Adjust contrast
3 4 RS Register select
4 5 R/W Read/Write
5 6 E Clock
7 D0
8 D1
9 D2
10 D3
6 11 D4 These pins
7 12 D5 > used for
8 13 D6 | 4 bit
9 14 D7 / operation